1. Field of the Invention
The invention relates to integrated circuit design and, in particular, to a lateral capacitor structure for an integrated circuit capable of mitigating capacitor mismatch.
2. Description of the Related Art
Many digital and analog elements and circuits have been successfully applied to semiconductor integrated circuits. Such elements may include passive components, such as resistors, capacitors, or inductors. Typically, a semiconductor integrated circuit includes a silicon substrate. One or more dielectric layers are disposed on the substrate, with one or more metal layers disposed in the insulating layers. The metal layers may be employed to form on-chip elements, such as on-chip metal-insulator-metal (MIM) capacitor, by current semiconductor technologies.
Conventionally, the on-chip MIM capacitor includes two flat conductive plates, with one parallel to and on the top of the other, and an intervening layer of dielectric material. Such a capacitor structure has a drawback of a larger required chip area. Moreover, additional lithography and etching for formation of the top plate results in increased manufacturing cost.
One approach to reduce the required chip area of the MIM capacitor involves the use of a layer of parallel interdigitated conductive lines as electrode plates having a dielectric material therebetween. Such a capacitor structure provides higher capacitance per unit area, as a result of the increased capacitance afforded by vertical MIM capacitors formed by the opposing top and bottom electrode plates, and lateral MIM capacitors formed by the adjacent electrode plates. FIG. 1 illustrates a conventional parallel interdigitated capacitor structure for an integrated circuit. The capacitor structure includes a dielectric layer 102 disposed on a semiconductor substrate 100. A conductive line pattern is embedded in a first level of the dielectric layer 102, comprising a plurality of parallel metal lines 105 separated by a predetermined space. The adjacent metal lines 105 have opposing polarity and are labeled by “+” and “−”. Another conductive line pattern is embedded in a second level of the dielectric layer 102 lower than the first level, comprising a plurality of parallel metal lines 103 separated by the predetermined space. The plurality of metal lines 103 is substantially aligned with the plurality of metal lines 105 and each metal line 103 has polarity opposed with the corresponding metal line 105, labeled by “+” and “−”. The adjacent metal lines 105 and the adjacent metal lines 103 form lateral capacitors, respectively, and the metal lines 105 and the corresponding metal lines 103 form vertical capacitors.
The metal lines 103 and 105, acting as electrode plates of capacitors, are typically formed by damascene technology. During formation of the metal lines 103 and 105 or planarization of the insulating layer 102, dishing is induced due to the effects of chemical mechanical polishing (CMP) on dielectric layer 102. MIM capacitor mismatch is worsened because the metal lines 103 and 105 are embedded in the uneven dielectric layer 102. As a result, the performance of integrated circuits is affected.
Thus, there exists a need in the art for an improved capacitor structure design capable of mitigating capacitor mismatch.